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多核虚拟可重构结构加速逻辑电路演化设计的研究

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提出了一种用基于多核虚拟可重构结构（MuViRaC）的内部演化硬件来加速组合逻辑电路演化设计过程的方法。其主要思想是依据增量演化中的输出函数分解策略，将一个组合逻辑电路分解为多个具有更少输出的子电路。每个子电路在MuViRaC上以两阶段并行演化的方式进行演化。MuViRaC在CeloxicaRCl000PCI板上的XilinxVirtexxcv2000EFPGA上实现。MuViRaC分别被应用于演化3位乘法器和3位加法器。试验结果证明MuViRaC能够有效地减少组合逻辑电路的演化代数和演化时间。

This paper presents a multi-virtual reconfigurable architecture cores （MuViRaC）-based intrinsic evolvable hardware （EHW） to speedup the evolutionary design of combinational logic circuits. The basic concept of the proposed scheme is to divide a combinational logic circuit into several sub-circuits according to the output function decomposition strategy for incremental evolution. Each sub-circuit is then evolved separately as a subcomponent through a two-stage parallel evolution process implemented on the MuViRaC. In this study, the MuViRaC was realized on a Xilinx Virtex xcv2000E FPGA that was fitted in a Celoxica RC1000 PCI board. The performance of the proposed scheme was evaluated on the...

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